Luke Wren @wren6991@types.pl Profile
Luke Wren @[email protected]

@wren6991

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Cursed computer architecture enthusiast. Engineer at Raspberry Pi. 日本語下手。 He/him

Cambridge, England
Joined December 2011
Don't wanna be here? Send us removal request.
Over 200 MiB of cache. If yall weren't so bad at programming we wouldn't even need SDRAM
@TechPowerUp
TechPowerUp
1 month
AMD Ryzen 9 9950X3D and 9900X3D to Feature 3D V-cache on Both CCD Chiplets
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@wren6991
Luke Wren @[email protected]
2 months
I finally have a legitimate use case for one of these awful HDMI to screw terminal adapters, I'm so excited
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@wren6991
Luke Wren @[email protected]
3 months
Didn't expect this level of sass from the libgcc soft float implementation
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I think there is a strong argument that a buffer should be called an OT gate 🤔
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I knew many oscilloscopes run Windows, but it really sank in today when I saw a coworker in the lab running a Webex conference call on one of the scopes. They were live-sharing the oscilloscope screen, whilst making changes to the circuit's input and discussing on the call
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When I run `ffmpeg --help` I distinctly feel my computer take a deep breath before it starts to explain
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Factorio players are optimising their belt balancers by reducing belt balancing to SAT and feeding to a SAT solver. Fucking incredible
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I'm a big fan of high-level languages, such as x86 assembly
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Yet again there is discourse about debuggers vs printf, but why don't more people use a waveform viewer to debug their software? Works for me
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Did some soldering yesterday
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Wow, apparently Factorio implements nonblocking autosave by literally calling fork() and then saving from the forked memory in the background. Game chugs for a bit because of all the copy-on-write penalties, but it avoids pausing the game for an autosave
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@wren6991
Luke Wren @[email protected]
2 months
PCB twisted pair
@hanai_y
天球儀
2 months
有効なのは分からんでもないけどもやもやするw
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@wren6991
Luke Wren @[email protected]
3 months
Datasheet is live: Hopefully we kept you all guessing on what the "3" stands for in RP235x! Cortex-M processors are clearly best-in-class, but I hope you have fun playing with my core too.
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Verilog is a wonderful language because you find things like this in the standard (1364-2005 5.4.2) How can you write something like this and not go "wait, go back, we fucked up"
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Good morning! Feel like bitbanging some DVI from my new microcontroller.
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PCB design is my passion
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@wren6991
Luke Wren @[email protected]
2 months
@jwt0625 I assume it is not rated for 13 amps at 240 VAC
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This whole slide deck is funny and informative, but this slide in particular I think needs to be printed out on my wall
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I wonder how many processors there are in an "empty" modern motherboard? At least one of them can run a USB + FS stack. How many of them are 8051s?
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The trolley problem has been solved!
@Btoretsukuru
B作
3 years
『トロッコ問題』で全員助かる方法 こんな答えはどうかな? #鉄道模型 #N ゲージ
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Really wish synthesis tools would stop warning you when they perform basic optimisations
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Who called it "jet lag" and not "clock domain crossing"
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I did a thing
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Periodically think about my first year dynamics + structures supervisor who used Matlab for photo editing Just loaded it in as a big matrix, did some operations to adjust brightness and contrast, saved back out as a JPG Definitely a Type Of Guy
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Tired: profiling Wired: toggle a GPIO on function entry and exit, measure the duty cycle
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@wren6991
Luke Wren @[email protected]
2 months
Weird how IEEE 754 only parameterises the number of exponent and significand bits. We should be allowed to have more sign bits too.
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@wren6991
Luke Wren @[email protected]
5 months
Upcoming Arm ThinkPad replaces PrintScreen with a copilot key. Replacing a useful key with a physical ad for LLM slop is a way to ensure I won't buy your product Hopefully when this bubble bursts we all go back to selling monkey JPEGs. It was an honest living, comparatively
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What's your favourite Python 3 operator? Mine is the w i d e operator
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Would love to have the confidence of the person who pasted an entire C header into an IEEE standard and labelled it as normative
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Multilayer boards are so beautiful before you flood the planes!
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@wren6991
Luke Wren @[email protected]
3 months
I just published the v1.0 release of Hazard3, my 3-stage RISC-V core. There aren't many new features, but there's a lot of cleanup and maintenance work that will make it a better platform for development going forward. Read the release notes here:
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If I could snap my fingers I would make the terms "Von Neumann architecture" and "Harvard architecture" disappear from every undergraduate course on computer architecture, until we decide whether they describe an architectural or microarchitectural decision
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@wren6991
Luke Wren @[email protected]
5 months
LPDDR5X-8533? My dude that is not synchronous DRAM, that is radio frequency DRAM
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Using ":-)" when emailing older coworkers is a form of code switching
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Don't recall who asked about 800x480p60 but yes it seems to work. Not sure how that image got there
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Actual line of C encountered in the wild: ((void (*)())0x10000101)(); It has everything: void, parentheses, 1s and 0s. It's like the e^(i pi) + 1 of C programming
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At last... the third boolean
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@wren6991
Luke Wren @[email protected]
3 months
The RP2350 ROM source being out means I can share two of my favourite functions: unpacking `bl` and `movw` immediates using RV32IBZbkb. It took a lot of squinting to get these right, I wonder if anyone can knock another cycle off? (Also it's a shame pack/packh aren't in Zbb!)
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Full shareware DOOM with multiplayer, 264 kB of RAM and 2 MB of flash! Looking forward to seeing the writeup 😃
@kilograham5
graham sanderson
3 years
Happy Pi Day! #RP2040 #Doom is here with the FULL DOS game experience 320x200 VGA, 9 channel music, sound effects, 1-4 players (I2C), USB keyboard, saved games, cheats, demos, all cut/end screens Fits all 9 shareware levels on 2M @RaspberryPi Pico! 1/4
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"Multi function gate" (squints) that is literally just a mux
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CPU ideas: - Bit-serial Itanium - Out of order superscalar 6502 (65OoO2) - 16-bit RISC-V ISA variant (RV16I) - Microcontroller with Cell SPEs - Jazelle DBX, but for Lua bytecode on RISC-V Free to a good home
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Designing a 16-bit serial processor for Tiny Tapeout 2. It jiggles its registers to save area. Very serious logic design.
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Thinking about the 86 people who bought this off Amazon
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Example of a 16-16 balancer found by the solver, shorter than the previous best known by 1 tile:
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Want to make a carrier board for @arturo182 's RP2040 Stamp that fits into an AliExpress Gameboy. Minimal circuitry for the first revision. I'm going with the meme solution of using the 2.5mm TRS jack as a debug connector so I don't have to open the case to debug it
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Writing some good code today
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@lindsey HW eng: so we have some CPUs with caches Verification eng: gotcha HWE: they implement atomic accesses, so sw can build locks etc VE: um HWE: every trillion cycles or so, a core gets starved VE: (hands shaking, opening whisky) HWE: so we randomly perturb state and retry the access
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Cat (and I cannot stress this enough) Printer
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This is the most exciting white text on a black background I have seen in a long time
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When academics use words like "A Primer" it means you're about to get the insides of your brain rearranged
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@wren6991
Luke Wren @[email protected]
3 months
New version of PicoDVI. Most of the Arm assembly in libsprite and libdvi is now ported to RISC-V. Adds support for the RP2350 TMDS encoders.
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The parts always look smaller on the schematic!
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It's crazy to me that formal solvers can write RISC-V programs without any innate knowledge of the instruction set. Just attach a memory, tell it to assume PC never leaves that memory, and it will write all programs with that property, to test my assertions
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I am enjoying the doom source
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Product idea: a multimeter with headphones, so you can beep out a circuit without pissing off everyone in the office
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Time for my annual reading of the J1 Forth CPU paper. It's just so pretty! The way the core, the architecture and the language tile together. I still haven't clocked how he bootstrapped the toolchain so quickly, starting to see why Forth is a cult classic
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posted without context
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Debugger acknowledges that my core is, in fact, a 32-bit RISC-V processor 🥳 they grow up so fast! (pic: openocd happily bitbanging JTAG in my CXXRTL sim through a TCP socket)
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I don't know who needs to hear this, but please stop writing string parsing in Verilog
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Also systems programming languages, such as udev rules
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A game I like to call "Factorio or FPGA floorplan" (source: )
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Seen some people mention the lack of DAC on RP2040, but you can DMA to the core supply voltage select register, so idk what they are complaining about
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Electronics diagrams that look like shitposts
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SDRAM easter eggs! 2-row tRC violation: copy entire rows of data within a subarray 3-row activation: compute bitwise functions Now, 4-row activation: generate true random numbers at Gb/s speeds Wonder what we unlock by activating 5 rows at once, maybe hidden RGB LEDs?
@SAFARI_ETH_CMU
SAFARI Research Group
3 years
Tomorrow Ataberk Olgun will present "QUAC-TRNG: High-Throughput True Random Number Generation Using Quadruple Row Activation in Commodity DRAM Chips" @ISCAConfOrg Wed June 16 Session 11A 1:15 pm EDT Paper: Slides(pdf): @_onurmutlu_
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This is the SoC I want to build on ULX3S over Christmas to prove out my global atomics, and maybe port some software. Christmas SoC. It's an odd bus architecture, but something I can cobble together without designing any significant new components, like uhhh coherent caches
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Is it a good idea? Absolutely not. But did I at least execute it well? Again, no
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@_Ninji @alt_kia Hardware XML parser implementations are a thing! I see papers popping up on r/FPGA every now and then with ominous references to "real-time XML parsing"
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Spent a lot of time wondering which is the greater evil out of the I2C standard, and I2C implementations. Overjoyed to say I have found a new contender: flow charts from I2C hardware documentation You can't have a decision box where the only option is "Y"???
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Out of curiosity, had a look at driving RP2040's pads open-drain for DVI, since it's closer to the current sink intended for TMDS. Left is the existing push-pull, right is open-drain, both at 252 Mbps (480p 60 Hz). Yeah that's a no 😅
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Tonight I realised that I had left the RISCBoy repo in a broken state, so I fixed that up. Some of these demos are moving a lot of pixels for 36 MHz! Maybe I need to go back and revisit this, I'm sure there are a lot of things I would do differently today.
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If you struggle to remember whether UARTs are MSB-first or LSB-first, here's a handy tip to figure it out: implement a UART, and the correct bit order is the opposite to what you implemented
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@wren6991
Luke Wren @[email protected]
11 months
Cortex-M3 Cortex-M3 Pro Cortex-M3 Max Cortex-M3 Ultra
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"standard" UART rates should be destroyed, just use divisions/multiples of 1 Mbaud you filthy animals
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That's now two people who have hooked up an HDMI connector directly to a breadboard and had it work flawlessly. Pump this shit straight into my veins
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The curse of looking at random pieces of hardware and thinking "you could fit an FPGA in there"
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Sudden urge to build a 2-stage RV32I. There is just something pleasing about 2-stages
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Yesterday I got a lint for "redundant subexpressions" my dude that is literally your job, you are a compiler
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@wren6991
Luke Wren @[email protected]
7 months
TIL the "D" in D-PHY doesn't stand for anything, it's a Roman numeral
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Best thing I've seen on the orange website so far
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@wren6991
Luke Wren @[email protected]
2 months
First time in Japan. It's true, these power lines do be hitting different
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Hey this looks pretty good in colour!
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I posted this as a joke, but there is truth in it. More than once I have had a processor pass RISC-V ISA compliance but fail to execute a nontrivial printf format. I have never seen the opposite.
When your processor runs `printf("%f\n", 1.23f);` with soft float it's ready to ship
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I saw from @arturo182 that they make a 100x100mm version of this hot plate (946-1010), which is just right for the boards I make, so I went ahead and ordered one. It goes down to 50°C, so I figure when I'm not soldering I can use it to keep my tea warm. Seems perfectly safe
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Good sign if you can get to blinky without reading the documentation! What a lovely board
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Haha PLL goes boingggg
@twi_kingyo
金魚
3 years
できたw といってもGPSモジュールが出す10MHz信号(CH2)とVCTCXOの信号(CH3)を位相比較してVCに与えているだけだが...  ループフィルタの帯域落としすぎてロックが遅いw
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Thinking again about this Super Metroid walkthrough where the text is perfectly justified through word choice alone
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@The6P4C I am so ready to spend an hour drawing different types of mechanical keyboard switch on the whiteboard. Not my fault they can't scope a question
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First post on cohost: "Designing a terrible processor in 6 days"
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@arturo182 you can see why we went to 40nm, the first ones were huge
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General-purpose CPU implemented with RP2040 DMA control lists:
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Had great fun talking to @AlessandroDevs and @fixxxxxxer yesterday! Here is one of the demos we shared: VGA + I2S + SD card media player running at 48 MHz thanks to @kilograham5
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Wait, that's a UART
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Take a drink every time the Verilog standard doesn't specify fundamental behaviour of some operator
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@the6p4c 2 types of hardware engineer
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*hits bong* what if the debug probe enumerated as a USB-ethernet device and just ran a debug translator and gdb server on-probe
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Making a thing I needed
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