Marcelo Samsoniuk @samsoniuk Twitter profile | Pikagi

Pikagi

Marcelo Samsoniuk

@samsoniuk

2,459

Followers

336

Following

1,153

Media

7,068

Statuses

#RISCV #DarkRISCV #680x0 #VLIW #DSP #FPGA #Verilog #C #AWK #VHDL #HPC #GPU #memes and #cyberpunk #jokes

Irvine, CA

https://t.co/SmgDpiTjWs

Joined December 2013

Don't wanna be here? Send us removal request.

Pinned Tweet

@samsoniuk

Marcelo Samsoniuk

2 months

... and that is! both L1 caches working in Harvard architecture on hit and time multiplexed in von Neumann architecture on miss! the CPI is not good as pure Harvard but far better than pure von Neumann, so now I have a very usable MC68040 replacement! 🔥

Tweet media one

2

1

15

Last Seen Profiles

@22333D

@sethemfreetr

@wdynwdyn1

@ozybicer

@fizctional

@orislp

@Tante_giranggg

@MassiveCoomer05

@zawawa2002

@ranya1313130

@UlkerCemre

@newsls

@Gorgeousbabe113

@tjichiro

@gartenjm13

@tsubuan_opn

@WindySaputrii1

@MIYAMOTOXIV

@BacaoRSB

@atlerudshaug

@RuruKigururu

@SivaKum56664767

@forchaebin

@CJR

@OwZ7f

@uyanisyayinevi

@sannetenwolde

@cantorabadabes

@yuyahat2000

@_yui_i7

@bokeplokalmalam

@4RENCHUU

@tunde_Gabe

@a4analyse

@toudaiou_tbs

@tsukasamiyoshi

@samsoniuk

Marcelo Samsoniuk

4 months

DDR is really not easy! check this post about UberDDR3, an open source DDR controller! 🔥

Tweet media one

6

67

442

@samsoniuk

Marcelo Samsoniuk

4 months

wow! "new" i860 book arrived here today! 🔥

Tweet media one

Tweet media two

Tweet media three

9

37

389

@samsoniuk

Marcelo Samsoniuk

2 months

wow! that is really crazy: a FPGA inside a micro-SD card! 🔥

Tweet card media

Getting Started with the Signaloid C0-microSD FPGA Platform

Learn how to configure and load bitstreams onto the C0-microSD's iCE40 FPGA across two example projects.

www.hackster.io

8

61

375

@samsoniuk

Marcelo Samsoniuk

2 years

too good to be true... 🤔

Tweet media one

24

54

334

@samsoniuk

Marcelo Samsoniuk

9 months

thanks, Vivado! 😅

Tweet media one

4

54

281

@samsoniuk

Marcelo Samsoniuk

2 years

#riscv is just cheap as sand! but be careful: 4.95$ for 50 pieces! so order "10" will result in 500 devices! 🔥

Tweet media one

5

33

260

@samsoniuk

Marcelo Samsoniuk

4 months

already posted here, but never gets old: the future of programming are neural networks on 10 cent processors! small problems on small devices, no need for a GPU everywhere…🔥

Tweet media one

3

42

259

@samsoniuk

Marcelo Samsoniuk

4 months

"FPGA Development Needs a Modern Refresh" this guy is really very funny! 😂

Tweet media one

21

19

244

@samsoniuk

Marcelo Samsoniuk

2 months

Harvard vs. von Neumann on #DarkRISCV : w/ Harvard there are two concurrent buses Yxxx for instructions and Xxxx for data, resulting in CPI=1.62, while w/ von Neumann they are time multiplexed to a single bus, resulting in a CPI=4.82, both w/ BRAM and no-caches! 🔥

Tweet media one

Tweet media two

5

37

233

@samsoniuk

Marcelo Samsoniuk

1 year

the truth about rust? it is just written in C/C++ and takes really a lot of time to compile... probably the largest C/C++ code that I compiled ever...save energy, save the planet, don't use rust! 🌎

Tweet media one

19

28

184

@samsoniuk

Marcelo Samsoniuk

1 year

another nice free book about parallel programming! 🔥 "Is Parallel Programming Hard, And, If So, What Can You Do About It?" -- Paul E. McKenney

Tweet media one

4

50

183

@samsoniuk

Marcelo Samsoniuk

1 year

It makes me sad to know that so many nice people suffer programming in rust... when you all want migrate to other easy language, such as C or asm, I'll be here to help! 💖

Tweet media one

21

19

180

@samsoniuk

Marcelo Samsoniuk

3 years

best amazon review ever! 🤣

Tweet media one

1

33

162

@samsoniuk

Marcelo Samsoniuk

1 year

do you want learn how to design soft-processors? start with this amazing presentation 1st! 🔥

Tweet media one

6

37

147

@samsoniuk

Marcelo Samsoniuk

3 months

well, it is time to make that SDRAM work! 🔥

Tweet media one

2

7

135

@samsoniuk

Marcelo Samsoniuk

2 months

people always ask: why is FPGA so slow?! well, it is all time, money, effort and tools! check how much effort IBM put on Cell development to make it work at 3GHz+ on 45nm vs. the effort put by a guy working on spare time around a Spartan-6 and similar 45nm... 😅

Tweet media one

8

10

120

@samsoniuk

Marcelo Samsoniuk

1 year

wow! look this NM27C256Q150 pic! 🔥 made with a 70 USD microscope from Aliexpress!

Tweet media one

6

10

117

@samsoniuk

Marcelo Samsoniuk

10 months

wow! 💖

Tweet media one

0

9

112

@samsoniuk

Marcelo Samsoniuk

2 months

lots of updates on DarkRISCV today! 🔥 1) new structured and modular SoC 2) the core requires < 1000 LUT6 3) new i/d caches, new async bus protocol 4) small caches keep a good CPI even w/ wait-states 5) working fine on real #FPGA !

Tweet media one

3

19

113

@samsoniuk

Marcelo Samsoniuk

2 years

the saddest day of the FPGA era: RIP Xilinx! 🔥

@sahajsarup

Sahaj Sarup 🐧

2 years

Very weird and oddly sad to see $AMD branded Zynq FPGAs, I was hoping they kept the Xilinx brand. I'm happy for the acquisition but sad to see the Xilinx name go away.

Tweet media one

9

30

309

5

15

106

@samsoniuk

Marcelo Samsoniuk

1 year

wow! kintex-7 K420T w/ typical dual-channel DDR3, 2xHDMI, 2xSFP+ and 2xQSFP+... also 8x PCIe endpoint + 8x PCIe root complex! this guy is really so f*cking good! 🔥

Tweet media one

5

4

103

@samsoniuk

Marcelo Samsoniuk

9 months

very simple cache logic, introduced back in 1984 with MC68020... it is very easy to implement and I used a 64x56-bit LUTRAM on darkriscv, with a measured hit ratio of 80% when running a small test firmware! 🔥

Tweet media one

1

9

97

@samsoniuk

Marcelo Samsoniuk

2 years

pic of the year! 🔥

Tweet media one

@hackinarticles

Hacking Articles

@hackinarticles

2 years

Pic of the Day #infosec #cybersecurity #cybersecuritytips #pentesting #oscp #redteam #informationsecurity #cissp #cybersecuritytips

Tweet media one

10

66

725

2

10

91

@samsoniuk

Marcelo Samsoniuk

9 months

wow! look this multitask and multiuser linux running on a home made RISCV, running on a cheap FPGA board: that is the future! 😁

@splinedrive

logic destroyer

9 months

This now feels like real Linux. I have my rootfs on the SD card; it boots from the SD card. I have two terminals, I have 64 MiB of memory. What more could you want? MicroPython, in the other terminal a RISC-V logo program, and a GPIO blinky as a process. KianV RISC-V Linux SoC

5

5

48

2

12

91

@samsoniuk

Marcelo Samsoniuk

1 year

worst hello world, ever! 😂

Tweet media one

6

6

78

@samsoniuk

Marcelo Samsoniuk

5 months

looks so professional that makes my eyes smile! <3

Tweet media one

@matthewvenn

Matthew Venn

5 months

Check out this cool 12 bit SAR ADC by Ricardo Nunes submitted to #TinyTapeout 7! Explore it yourself: Project link:

5

22

127

0

10

78

@samsoniuk

Marcelo Samsoniuk

4 months

although not a vector processor, the i860 (1989) was called "cray on a chip" because it was supposed to peak the same performance as a cray-1 (1975)... also interesting, the block diagrams for both are in the same style! 🔥

Tweet media one

Tweet media two

5

8

77

@samsoniuk

Marcelo Samsoniuk

2 months

and, to finish the day, we had this nice slice w/ an amazing image from a 1Tbps transceiver, composed by 304 packed LEDs and 304 packed PDs, each one in only 50μm! 🔥

Tweet media one

@samsoniuk

Marcelo Samsoniuk

2 months

wow! we are online now! 😉

Tweet media one

0

1

18

0

5

77

@samsoniuk

Marcelo Samsoniuk

2 years

that daily Vivado joke... 😂

Tweet media one

@memenetes

memenetes

2 years

everyone loves free stuff

Tweet media one

3

123

923

1

14

74

@samsoniuk

Marcelo Samsoniuk

1 year

just an old C trick w/ pointers!🔥

Tweet media one

3

10

67

@samsoniuk

Marcelo Samsoniuk

9 months

wow! I am connected to @splinedrive 's FPGA based multi-user linux SoC via ethernet and it is working really fine! 🔥

Tweet media one

3

9

67

@samsoniuk

Marcelo Samsoniuk

6 months

wow! look that huge L1 cache! 🔥

Tweet media one

6

8

67

@samsoniuk

Marcelo Samsoniuk

7 months

wow! this small header can change the entire future of C programming! not sure the code works, but the syntax is very crazy! 😂

Tweet media one

12

4

64

@samsoniuk

Marcelo Samsoniuk

1 year

wow! 5 years of DarkRISCV! 🔥 thanks @splinedrive by the link w/ ASCII badapple! it was originally 15MB, scalled down 1/16 to 900KB and compressed it w/ RLE to 100KB, but cut 1/4 of the video in order to fit on a small LX9! 🎉

4

7

63

@samsoniuk

Marcelo Samsoniuk

8 months

wow! congratulations Altera! 💖

Tweet media one

2

9

64

@samsoniuk

Marcelo Samsoniuk

3 years

Wow! The new 100USD #Kintex7 K325 coreboard from #QMtech worked fine with the DarkRISCV @250MHz and the baseboard from the #Artix7 A35 set... [in theory] is possible fit around 100 #DarkRISCV cores running up to 250MIPS in this #FPGA , which means [in theory] 250MIPS/USD! 🥳

Tweet media one

6

11

61

@samsoniuk

Marcelo Samsoniuk

1 year

wow! I lost my job designing #riscv cores! 😅

@tomshardware

Tom's Hardware

1 year

Chinese Researchers UsedAI to Design Industrial-Scale RISC-V CPU in Under 5 Hours

Tweet media one

0

14

50

3

4

59

@samsoniuk

Marcelo Samsoniuk

3 months

wow! we finally have "ebreak" on darkriscv! 🔥

Tweet media one

2

7

60

@samsoniuk

Marcelo Samsoniuk

2 months

well, I developed something like RIOS almost 20 years ago for the HC908! so thanks to the RIOS article, I found motivation to locate the original repo and make it available 'as is' on the github! 🔥

Tweet media one

@samsoniuk

Marcelo Samsoniuk

2 months

interesting article about RIOS RTOS! 🔥

Tweet media one

2

3

41

1

5

59

@samsoniuk

Marcelo Samsoniuk

1 year

thanks @splinedrive for the tip! here is a compact DDR3 controller (9% of an Artix A35) that can run with smaller clocks (<=125MHz)! just to compare, a Xilinx MiG requires 33% of area in a same FPGA and 300MHz+ clocks! 🔥

Tweet card media

GitHub - ultraembedded/core_ddr3_controller: A DDR3 memory controller in Verilog for various FPGAs

A DDR3 memory controller in Verilog for various FPGAs - ultraembedded/core_ddr3_controller

4

9

58

@samsoniuk

Marcelo Samsoniuk

2 years

step by step AES implementation in verilog 🔥

2

7

57

@samsoniuk

Marcelo Samsoniuk

7 months

wow! the DarkRISCV and other RISCV cores were evaluated against other opensource cores! take a look on the paper! 🔥 #innovation #poweredby #riscv

Tweet media one

1

11

56

@samsoniuk

Marcelo Samsoniuk

6 months

the wiring between the core and the cache is really insane! thanks @duke_cpu 💖

Tweet media one

1

1

54

@samsoniuk

Marcelo Samsoniuk

4 months

well, risc-v is too mainstream now, so it is time to work on risc-vi! 😂

Tweet media one

9

4

52

@samsoniuk

Marcelo Samsoniuk

4 months

wow! some additional info about the lost "FPGA" book that I found here! the cells are very different but do the job almost the same way... lots of interesting stuff and applications! for more please check the online copy 🔥

Tweet media one

Tweet media two

Tweet media three

1

3

52

@samsoniuk

Marcelo Samsoniuk

7 months

this old presentation is very epic! 🔥 I can just look for my job and confirm: small ASICs had no much chance against small FPGAs in the last 20 years! 😁

Tweet media one

5

2

52

@samsoniuk

Marcelo Samsoniuk

4 months

wow! this is pretty weird! 🔥

Tweet media one

3

8

49

@samsoniuk

Marcelo Samsoniuk

2 months

wow! #DarkRISCV is SIX years old today! 🎉 it was introduced on Github on Aug 19 and, 10 days later, my friend Guilherme Barille posted about it on HackerNews, which was noticed by Alasdair Allan and that wrote a very iconic article about it! 🔥

Tweet media one

2

9

49

@samsoniuk

Marcelo Samsoniuk

8 months

@hansfbaier well, that was not exactly correct, so I fixed it to match with our actual FPGA applications! 🤣

Tweet media one

4

6

49

@samsoniuk

Marcelo Samsoniuk

4 months

for old school people interested on a good non-linux unix-like with high performance on embedded FPGA: try #xv6 🥇

Tweet media one

@splinedrive

logic destroyer

4 months

@X @samsoniuk If you're interested in getting xv6 running on the Colorlight board, here are some demo images. There's no code included yet because I'm still figuring out how to merge Linux and xv6 in the code. Additionally, I plan to rework the SoC so that we have a unified version for

0

0

4

1

10

49

@samsoniuk

Marcelo Samsoniuk

4 months

the most expensive LED blinker: darkriscv core running at 100MHz on a xilinx spartan-6, with 1M interrupts per second in order to feed a software timer and blink a LED w/ microsecond speed! 💸

Tweet media one

Tweet media two

0

3

48

@samsoniuk

Marcelo Samsoniuk

2 years

wow! my new x86 disk server is working! the correct disks did not arrived yet: 2x4TB 2.5" disks! also, I will need a 90 degree PCIe adapter in order to fit an FPGA-based network switch with 8x10Gbps ports! 🔥

Tweet media one

Tweet media two

Tweet media three

5

7

46

@samsoniuk

Marcelo Samsoniuk

1 year

wow! this is f*cking crazy: a soviet x86-based PC w/ a VME-like backplane! 🔥

Tweet media one

Tweet media two

Tweet media three

1

8

46

@samsoniuk

Marcelo Samsoniuk

4 months

I am posting this just to make some people cry! 🤣

Tweet media one

2

4

45

@samsoniuk

Marcelo Samsoniuk

4 months

since is very hard to click the link on the picture, there is the link! 😅

GitHub - riadhbenabdelhamid/BRISKI: BRISKI ( Barrel RISC-V for Kilo-core Implementations ) is a...

BRISKI ( Barrel RISC-V for Kilo-core Implementations ) is a fast and compact RISC-V barrel processor core that emphasize high throughput and compute density to increase the amount of cores in many-...

@jangray

Jan Gray

4 months

This work tops SERV for most *harts* per FPGA and rivals GRVI Phalanx for peak MIPS per FPGA. BRISKI employs HW multithreading well to achieve high Fmax, latency tolerance, and a clean frugal datapath. Riadh will soon present the kilocore SoC architecture at FPGA Europe (IIRC).

Tweet media one

0

3

21

0

5

45

@samsoniuk

Marcelo Samsoniuk

1 year

@R0b0tSp1der wait! brutal? oh my friend, I design processors with VHDL, that is really brutal! C and asm are sweet languages... no RAM memory? boot with only registers? fine, that is like a park walk on a sunny day! 😂

1

1

45

@samsoniuk

Marcelo Samsoniuk

4 years

What about FPGA overclock?! Ignoring the Vivado recommendation, I overclocked the DarkRISCV at 400MHz in this new KU040 board and it is working fine! Except by an overflow in the frequency register w/ 144MHz, but the 1us timer shows the correct divisor "399" 😂

Tweet media one

Tweet media two

4

12

45

@samsoniuk

Marcelo Samsoniuk

5 months

well, another Spartan-6 board w/ lots of blue LEDs working w/ #darkriscv ... I liked this board because it is powered by the USB serial console cable and include SDRAM and EEPROM memories! 🔥

Tweet media one

Tweet media two

Tweet media three

4

2

44

@samsoniuk

Marcelo Samsoniuk

3 months

aww, malloc/free bugs are so 90s… 🥹

@shobhitic

Shobhit Bakliwal

3 months

C gang

123

3K

24K

4

2

40

@samsoniuk

Marcelo Samsoniuk

2 years

wow! is time to move everything to #riscv ?! "Arm Changes Business Model – OEM Partners Must Directly License From Arm -- No More External GPU, NPU, or ISP’s Allowed In Arm-Based SOCs"

Arm Changes Business Model – OEM Partners Must Directly License From Arm

No More External GPU, NPU, or ISP’s Allowed In Arm-Based SOCs

www.semianalysis.com

3

8

43

@samsoniuk

Marcelo Samsoniuk

11 months

wow! take a moment to read about the amazing ZipCPU guy saga to implement a 10GbE interface on FPGA! 🔥

Tweet media one

@zipcpu

Zip CPU

11 months

Today's blog article discusses the 10Gb Ethernet switch project I've been working on, walking through the various stages used to handle network packets. True to form, it also discusses some bugs encountered along the way.

3

9

64

0

8

42

@samsoniuk

Marcelo Samsoniuk

3 months

another open source RISC-V... oh, wait! this amazing bit-serial RISC-V can scale between 1 to 8 bits per chunk! 🔥

Tweet media one

0

5

42

@samsoniuk

Marcelo Samsoniuk

1 year

testing a new 68k-like loop instruction on DarkRISCV: decrement, test, branch when zero in a single clock, plus 2 delay slots to increase even more the performance! 🔥

Tweet media one

Tweet media two

1

5

41

@samsoniuk

Marcelo Samsoniuk

1 year

wow! DarkRISCV finally runs on Cyclone 10LP: 3kLUT4 @50MHz and RMW cycles! 🔥

Tweet media one

Tweet media two

1

3

41

@samsoniuk

Marcelo Samsoniuk

5 months

1) check about vexriscv, no need to read the code, just check the concepts! 2) check this paper about how put 100 vex on a FPGA 3) check this video about 400 GRVI on a FPGA!

Tweet card media

Tues1215 - GRVI Phalanx A Massively Parallel RISC-V FPGA Accelerator...

www.youtube.com

2

5

41

@samsoniuk

Marcelo Samsoniuk

1 year

the 32-bit #riscv -like test ALU, but on different FPGAs: Kintex-7, Artix-7, Spartan-6 and Spartan-3E... really not bad! 🔥

Tweet media one

0

6

41

@samsoniuk

Marcelo Samsoniuk

2 months

the #DarkRISCV 's 6th anniversary is approaching, so I am rushing to clean up the structure and add new features! by now, I fully separated the chaotic and monolithic DarkSoCV module in lots of separated modules, in order to make it more easy to expand it in the future! 🔥

Tweet media one

1

9

40

@samsoniuk

Marcelo Samsoniuk

2 months

interesting article about RIOS RTOS! 🔥

Tweet media one

2

3

41

@samsoniuk

Marcelo Samsoniuk

3 months

wow! very interesting concept from Groq: tensor operands and results streams horizontally, instructions flows vertically!? hmmmmm... 🚀

Tweet media one

2

4

39

@samsoniuk

Marcelo Samsoniuk

4 months

wow! stop everything and read this interesting paper comparing lots of opensource cores at 130nm, including the well known #darkriscv , #vexriscv , #picorv32 and #SERV ! 🔥

Tweet media one

4

10

37

@samsoniuk

Marcelo Samsoniuk

4 months

“building a new kernel everyday keeps the zeroday hacker away” 😂

@splinedrive

logic destroyer

4 months

Don't fuck with Linux systems engineers. The KianV RISC-V Linux SoC, running the latest stable Linux kernel 6.9.6, was published today :)

Tweet media one

23

107

1K

0

2

36

@samsoniuk

Marcelo Samsoniuk

2 years

I will never be sure, but they are essential for inter-chip synchronous connection: change data on positive edge, sample on negative edge! 🔥

Tweet media one

@hansfbaier

Hans Baier @[email protected]

2 years

Just added support for negative clock edge flip flops in nextpnr-xilinx.

1

3

23

6

7

35

@samsoniuk

Marcelo Samsoniuk

2 years

#DarkRISCV easy way: just git it from , enter in the sim directory and run make! you need #iverilog in the path and, case you have #gtkwave , you can use the VCD file and see the 3-stage pipeline working! ❤️

Tweet media one

Tweet media two

0

8

36

@samsoniuk

Marcelo Samsoniuk

2 years

700 million dollars to develop a 2nm chip! 🤯

@IanCutress

𝐷𝑟. 𝐼𝑎𝑛 𝐶𝑢𝑡𝑟𝑒𝑠𝑠

2 years

$724.8m to develop a 2nm chip. #marvell2022iaday

Tweet media one

5

19

95

4

8

33

@samsoniuk

Marcelo Samsoniuk

2 years

I think Zynq is more like a duck... except that the duck does not try sell chips to you! 😂

Tweet media one

Tweet media two

2

3

34

@samsoniuk

Marcelo Samsoniuk

5 months

hmmm... why PA-RISC? 🔥 what if Commodore had not gone bankrupt?

Tweet media one

6

6

33

@samsoniuk

Marcelo Samsoniuk

2 years

wow! it works! I got the short PCIe cable (15 cm) just to fit the small gap and change the board angle, but a smaller 1.5 cm cable would work too... tested w/ a hi-end PCIe 16x video board, so probably it will work fine w/ FPGA and network cards too 🚀

Tweet media one

2

4

33

@samsoniuk

Marcelo Samsoniuk

4 months

wow! remember this next time you build a huge FPGA: Vivado it is not the best or faster tool but is far better than nothing! 😅

Tweet media one

2

5

33

@samsoniuk

Marcelo Samsoniuk

3 years

@OlofKindgren wow! did you remember how to use linked lists? after some years working with Verilog, I am unable to use anything else Verilog-like structures, such as caches, lookup tables and asynchronous req/ack flags! 😅

Tweet media one

4

3

33

@samsoniuk

Marcelo Samsoniuk

1 year

modern computer: 100% of CPU to produce no useful work! 😵

@badamczewski01

Bartosz Adamczewski

@badamczewski01

1 year

The year is 2023, and we no longer can make computers that function at all:

Tweet media one

217

251

4K

2

5

31

@samsoniuk

Marcelo Samsoniuk

1 year

@citifax @lucasteske for people asking how much time to erase...

Tweet media one

2

5

31

@samsoniuk

Marcelo Samsoniuk

2 years

be careful about those NILINX FPGAs! 🚨

@samsoniuk

Marcelo Samsoniuk

3 years

these f*cking guys have no limits! 😆

Tweet media one

0

0

14

3

2

31

@samsoniuk

Marcelo Samsoniuk

2 months

"Cell Architecture Explained" 🔥

Tweet media one

2

0

32

@samsoniuk

Marcelo Samsoniuk

2 years

"The graphics chip was codenamed Napalm, packed in about 14 million transistors, and was built on the 250nm process" -- @splinedrive what about do this in a FPGA? the K325T is a 28nm chip that is equivalent to 30M+ transistors! 😅

Tweet card media

3dfx Voodoo 5 6000 recreated via reverse engineering

This quad VSA-100 GPU flagship graphics card was never commercially released.

5

4

31

@samsoniuk

Marcelo Samsoniuk

1 year

it is funny how those dummy people from twitter does not know that X was already invented by MIT almost 40 years ago! 😂

Tweet media one

@lindayaX

Linda Yaccarino

1 year

X is the future state of unlimited interactivity – centered in audio, video, messaging, payments/banking – creating a global marketplace for ideas, goods, services, and opportunities. Powered by AI, X will connect us all in ways we’re just beginning to imagine.

12K

6K

34K

3

5

29

@samsoniuk

Marcelo Samsoniuk

1 year

@lucasteske eh a magica do radio: soh funciona bem se vc estiver sozinho na frequencia e a 1m de distancia da antena! 😁

1

0

31

@samsoniuk

Marcelo Samsoniuk

2 years

electromechanical computer from 1955! 🤯

@kenshirriff

Ken Shirriff

2 years

The Bendix Central Air Data Computer (CADC) is an amazing electromechanical device that computed airspeed, altitude, and other "air data" for fighter planes such as the F-104 and F-111. Digital computers weren't good enough in 1955, so the CADC used gears, cams and synchros.🧵

Tweet media one

25

213

1K

1

1

30

@samsoniuk

Marcelo Samsoniuk

2 years

@suarezvictor @GwenhaelG @enjoy_digital @BrunoLevy01 @splinedrive after start synth, you can create memes! 😂

Tweet media one

5

4

29

@samsoniuk

Marcelo Samsoniuk

1 year

wow! after almost one decade lost, I released again a small 16-bit core from the past! it is very crude, but uses only 322 LUTs and can run at 80MIPS with IPC = 1 🔥

GitHub - darklife/udarkrisc: u[Dark]RISC -- "micro-darkrisc" -- an early 16-bit micro-RISC proces...

u[Dark]RISC -- "micro-darkrisc" -- an early 16-bit micro-RISC processor defined before DarkRISCV - darklife/udarkrisc

2

7

30

@samsoniuk

Marcelo Samsoniuk

2 years

wow! DarkRISCV working in the ICE40 FPGA! amazing work, thanks @splinedrive ! 🔥

@splinedrive

logic destroyer

2 years

@samsoniuk #darkriscv #riscv on #lattice #ice40 on fire 50MHz maybe more possible. Full power pipelining cpu all night long...

1

1

13

1

3

28

@samsoniuk

Marcelo Samsoniuk

2 years

Vivado bug of day: I just added the configuration memory device and Vivado suggested a "fpga.bin"... after some hours, found that the suggested path was from the previous project, pointing to a different FPGA model! 🔥

Tweet media one

2

2

27

@samsoniuk

Marcelo Samsoniuk

2 months

IEEE's Hot Chips will start tomorrow! :O

Advance Program

A Symposium on High Performance Chips

1

4

28

@samsoniuk

Marcelo Samsoniuk

1 year

8192 operations per clock at 425MHz w/ 2-bit precision! 🔥

@HPC_Guru

HPC Guru

1 year

A brain-inspired chip from @IBM , dubbed #NorthPole , is more than 20 times as fast as - and roughly 25 times as energy efficient as - any microchip currently on the market when it comes to #AI tasks #HPC via @IEEESpectrum

Tweet media one

1

9

42

1

5

28

@samsoniuk

Marcelo Samsoniuk

1 year

wow! happy birthday Patrick! I worked w/ slackware the last 30 years and, even now, I use it to host the FPGA tools that are designed the future of the embedded computing! 🎉 thanks @volkerdi

Tweet media one

2

4

28

@samsoniuk

Marcelo Samsoniuk

10 months

... and that is why FPGAs are not so popular on HPC: Vivado is larger and requires more processing power than most HPC applications! 😁

Tweet media one

3

0

28

@samsoniuk

Marcelo Samsoniuk

7 months

wow! I was checking about the Fairlight CMI design and found something really amazing for a musical instrument designed in 1979: a dual-6800 @1MHz in SMP configuration! 🔥

Tweet media one

1

1

27

@samsoniuk

Marcelo Samsoniuk

1 year

@IntelFPGA DarkRISCV @50MHz on Intel Cyclone 10LP! 💖

Tweet media one

1

3

27

@samsoniuk

Marcelo Samsoniuk

1 year

python vs C running on a microcontroller at 16MHz... guess who is faster! 🤣

@thembeddevguy

The Developer Guy

1 year

One of them runs Python, the other runs baremetal C. Both microcontrollers run at 16 MHz. Both microcontrollers are given a simple task: toggle a LED. We will explore the topic "overhead" in a video soon!

Tweet media one

20

39

562

2

2

26

@samsoniuk

Marcelo Samsoniuk

8 months

wow! stop everything else now and look this amazing page about concurrency programming in C! 🙀 thanks leo! 🍕

Scheduling Internals

Wait, but how does async even work? (Animated)

0

5

26

@samsoniuk

Marcelo Samsoniuk

7 months

welcome to the future! 💥

Tweet card media

Improvements to static analysis in the GCC 14 compiler | Red Hat Developer

I work at Red Hat on GCC, the GNU Compiler Collection. For the last five releases of GCC, I've been working on -fanalyzer, a static analysis pass that tries to identify various problems at

developers.redhat.com

3

2

27